DesignCon Recognizes More than 40 Professionals with 2016 Best Paper Awards

DesignCon 2017 to Open Call for Proposals in Mid-May

Apr 21, 2016

SAN FRANCISCO, April 21, 2016 /PRNewswire/ -- DesignCon, the premier conference for chip, board and systems design engineers in the high-speed communications and semiconductor communities, today announced recipients of its Best Paper Awards following a successful DesignCon 2016. Each of these winners are being awarded for their outstanding contribution to the educational goals of the DesignCon program. DesignCon's 2016 event commenced January 19-21 in Santa Clara, CA. To view the full list of winners, visit:


 The 2016 DesignCon Best Paper Award winners have been chosen through a two-pronged judging process. First the DesignCon Technical Program Committee, comprised of leading experts in the electronic design space, reviewed all papers for originality, relevance, impact and quality. The resulting finalists were then judged based on the impact of their presentations, derived from attendee feedback collected at DesignCon 2016.

Winning papers fall into four design categories: High-Speed Signal Design, Memory & Parallel Interfaces, Test & Measurement, and Power Integrity…and the winners are:

High-Speed Signal Design

A Versatile Spectrum Shaping Scheme for Communicating Beyond Notches in Multi-Drop Interfaces

  • Kiarash Gharibdoust, EPFL
  • Ali Hormati, Kandou Bus
  • Amin Shokrollahi, Kandou Bus
  • Armin Tajalli, Kandou Bus
  • Christoph Walter, Kandou Bus

Mid-Frequency Noise Coupling Between DC-DC Converters and High-Speed Signals

  • Gustavo Blando, Oracle
  • Laura Kocubinski, Oracle
  • Istvan Novak, Oracle

Memory & Parallel Interfaces

Analysis and Verification of DDR3/DDR4 Board Channel Impact on Clock Duty-Cycle-Distortion (DCD)

  • June Feng, Altera Corporation
  • GaWon Kim, Altera Corporation
  • Marjan Mokhtaari, Altera Corporation
  • Balaji Natarajan, Altera Corporation

Optimal DDR4 System with Data Bus Inversion Feature in FPGA High Speed High Bandwidth Memory Interface

  • Penglin Niu, Xilinx
  • Changyi Su, Xilinx
  • Thomas To, Xilinx
  • Juan Wang, Xilinx
  • Yong Wang, Xilinx

Test & Measurement

Jitter, Noise Analysis and BER Synthesis on PAM4 Signals on 400 Gbps Communication Links

  • Maria Agoston, Tektronix
  • Mark Guenther, Tektronix
  • Kalev Sepp, Tektronix
  • Pavel Zivny, Tektronix

BER- and COM-Way Channel Compliance Evaluation: What are the Sources of Difference?

  • Vladimir Dmitriev Zdorov, Mentor Graphics
  • Chuck Ferry, Mentor Graphics
  • Cristian Filip, Mentor Graphics
  • Alfred Neves, WildRiver Technology

A New Characterization Technique for Glass Weave Skew Sensitivity

  • Eric Bogatin, Teledyne LeCroy
  • Vidyadhar Deodhar, University of Colorado, Boulder
  • Bill Hargin, Nanya
  • Vinit Sonawane, University of Colorado, Boulder
  • Anand Ursekar, University of Colorado, Boulder

Power Integrity

Impacts of Dynamic Noise in Multi-Core or SOC Designs

  • Dan Oh, Altera Corporation
  • Yujeong Shim, Altera Corporation

Electrical and Thermal Consequences of Non-Flat Impedance Profiles

  • Jae Young Choi, Oracle Corporation
  • Ethan Koether, Oracle Corporation
  • Istvan Novak, Oracle Corporation

Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices

  • Chan-Seok Hwang, Samsung Electronics
  • Sangnam Jeong, Samsung Electronics
  • Hyo-Soon Kang, Samsung Electronics
  • Jinwon Kim, Samsung Electronics
  • Daehee Lee, Samsung Electronics
  • Junho Lee, Samsung Electronics
  • Jong-Bae Lee, Samsung Electronics
  • Jieun Park, Samsung Electronics
  • Jinsung Youn, Samsung Electronics

To view the entire list of recipients, including individual researchers, please visit:

"We are pleased to recognize these exceptional papers as the best of the impressive presentations provided to attendees of DesignCon 2016," said Naomi Price, DesignCon Conference Content Director. "This awards program inspires researchers to consistently submit the highest-quality, ground-breaking content at DesignCon, year after year. Congratulations to all finalists and winners."

DesignCon 2017 Call for Papers
DesignCon will return to the Santa Clara Convention Center January 31- February 2, 2017. Call for Proposals will open in mid-May with all submissions due by the July 13, 2016 deadline. To stay updated on next year's event, visit:

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Twitter: @UBMDesignCon 

About DesignCon
DesignCon is the world's premier conference for chip, board and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board and systems designers in the country.  This three-day technical conference and expo combines technical paper sessions, tutorials, industry panels, product demos and exhibits from the industry's leading experts and solutions providers. More information is available at: DesignCon is organized by UBM Americas, a part of UBM plc (UBM.L), an Events First marketing and communications services business. For more information, visit

Kimberly Samra
DesignCon PR

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